1. Field of the Invention
The present invention relates to a circuit for controlling an equalization pulse width, and in particular, to a circuit for controlling an equalization pulse width that equalizes an input/output line without affecting an operational speed.
2. Background of the Related Art
A related art delay circuit 30 is used for forming an equalization pulse width using a metal option. As shown in FIG. 1, the delay circuit includes a pulse generator 10 that forms a pulse width in accordance with a set option when address signals ADD0 through ADDn are transited. An addition unit 20 receives and combines the pulses formed at each address, and an optional delay unit 30 adjusts the equalization pulse width.
The operation of the related art circuit for controlling an equalization pulse width will now be described. First, the pulse generator 10 detects the time when the address signals ADD0 through ADDn are transited and forms a predetermined pulse width based on the set option.
The addition unit 20 sums the thusly formed signals and forms one equalization pulse. The widths of the equalization pulses are adjusted using the optional delay unit 30.
As described above, the related art delay circuit has various disadvantages. The delay circuit 30 used to form a proper or desired equalization pulse width using the metal option has the pulse width determined by a repeated simulation under various simulation conditions (e.g., worst/typical/best speed). A speed delay problem occurs when expanding the pulse width to secure a predetermined operational safety timing margin. In addition, when narrowing the pulse width to increase the speed, as shown in FIGS. 2A through 2C, since a glitch does not surround the equalization signal EQ, an operational stability is decreased. In this case, a normal Y-selection signal NYS and a redundancy Y-selection signal RYS may be over-lapped, and a glitch problem may occur as shown in FIG. 2D so that a speed may be delayed and a data may be inverted because of an invalid data output.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the present invention is to provide a circuit for controlling an equalization pulse width that substantially overcomes one or more of the problems caused by disadvantages in the related art.
Another object of the present invention is to provide a circuit for controlling an equalization pulse width that stabilizes data and minimizes a speed delay.
Another object of the present invention is to provide a circuit for controlling an equalization pulse width that equalizes an input/output line.
Another object of the present invention is to provide a circuit for controlling an equalization pulse width that controls an equalization pulse without reducing an operational speed when a redundancy selection signal is generated and an overlap with a normal selection signal or glitch occurs.
To achieve at least the above objects in a whole or in parts, there is provided a circuit for controlling an equalization pulse width according to the present invention that includes a pulse generator for forming a predetermined pulse width in accordance with a set option when address signals are transited, an addition unit for combining pulses formed at each address signals, and a latch unit for continuously latching an equalization signal in an enabled state when signals are all enabled using a signal by which a redundancy Y-selection signal is enabled when a redundancy occurs in a coding signal from a Y-predecoder.
To further achieve the above objects in a whole or in parts, an equalization pulse control circuit according to the present invention is provided that includes a pulse generator that detects address signal transitions and generates corresponding pulse signals in accordance with a set option, an addition unit that combines the pulse signals formed using each of the address signals to output an equalization pulse and a pulse latch unit that continuously latches an equalization signal in an enabled state when the pulse signals are all enabled using a latching signal that enables a redundant Y-selection signal when a redundancy occurs in a Y-coding signal.
To further achieve the above objects in a whole or in parts, an equalization pulse control circuit according to the present invention is provided that includes a pulse generator that generates pulse signals based on a first signal transition, a unit that combines the pulse signals to output an equalization pulse and a pulse latch unit that latches an equalization pulse state based on first and second selection signals to output an equalization signal.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.